Official government website of the Government of Kingdom of Saudi Arabia
Link to official Saudi websites end with edu.sa

All links to official educational websites in the Kingdom of Saudi Arabia end with sch.sa or edu.sa

Government websites use the HTTPS protocol for encryption and security.

Secure websites in the Kingdom of Saudi Arabia use the HTTPS protocol for encryption.

Registered with the Digital Government Authority under number:

20250417892
Main
UQU Programs

Digital Circuit Design

EE2203
4 hours English

Digital Circuit Design

Digital Circuit Design
EE2201 Basics of Electric Circuits
4 hours Two requisites
1 Introduction Logic Design
2 Boolean System &Simple Logic Circuit Design
3 Boolean Algebra theory & Gate Minimization
4 K-Map Minimization
5 Quine McClusky Method
6 Multi-level NAND/NOR Circuits
7 Combinational logic gate design I
8 Combinational logic gate design II
9 Sequential Circuits
10 Latches and Flip-flops
11 State-diagram Design
12 State Machine and Sequence Detector
1.1 Mapped to: KLO1

Describe the binary, octal and hexadecimal number system, their mutual conversion and simple arithmetic

Teaching Strategy Traditional lecture
Assessment Methods Quizzes + Final Exam Question+ HW Assignments + Major Exam Questions
1.2 Mapped to: KLO1

Describe the logic gates, truth table, clock diagram and development of logic circuits with given information

Teaching Strategy Traditional lecture
Assessment Methods Quizzes + Final Exam Question+ HW Assignments + Major Exam Questions
1.3 Mapped to: KLO1

Illustrate Karnough-mapping and apply for gate level minimization for given sum-ofproduct and product-of-sum circuit

Teaching Strategy Traditional lecture
Assessment Methods Quizzes + Final Exam Question+ HW Assignments + Major Exam Questions
1.4 Mapped to: KLO1

Describe the logic function and their implementation with minimal hardware.

Teaching Strategy Traditional lecture
Assessment Methods Quizzes + Final Exam Question+ HW Assignments + Major Exam Questions
2.1 Mapped to: KLO2

Design and analyse different combinational circuits with given time delays and minimum gate level minimization

Teaching Strategy Traditional lecture
Assessment Methods Final Exam Questions
2.2 Mapped to: KLO2

Design and analyse medium scale integration (MSI) logical circuits

Teaching Strategy Traditional lecture
Assessment Methods Final Exam Questions
2.3 Mapped to: KLO2

Design and analyse various types of counters

Teaching Strategy Traditional lecture
Assessment Methods Final Exam Questions
3.1 Mapped to: KLO8

Demonstrate the importance of and engage in Life-long learning

Teaching Strategy Term Paper
Assessment Methods Term Paper Report
3.2 Mapped to: KLO8

Conduct professionally and responsibly.

Teaching Strategy Classroom Participation
Assessment Methods Discussions
3.3 Mapped to: KLO 3, 7, 8

Handle tools and materials and apply rules for equipment & personal safety.

Teaching Strategy Lab Experiments + Mini Project
Assessment Methods laboratory experiments, Lab reports, and final lab exam
Assessment
Weight
Classroom Participation
5%
HW Assignments
5%
Quizzes
10%
Major Examination
10%
Experimental lab / Lab Final Exam
20%
Final Examination
50%
Total
100%